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8366cdd22448548116b4cc2f719fee73f8c30e91
hakurei/internal/rosa/package/spirv/0014-SPV_EXT_split_barrier-600.patch
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cat 8366cdd224 internal/rosa/package/spirv: spirv-tools 2026.1 to 2026.2 
Upstream does not appear to understand the point of tags, so include relevant unreleased changes here.

Signed-off-by: Ophestra <cat@gensokyo.uk>
2026-07-15 14:35:10 +09:00

367 lines
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From fe44b2002bf7871e2e92fc001bc9f6e09f92194f Mon Sep 17 00:00:00 2001
From: Ralph Potter <r.potter@samsung.com>
Date: Thu, 14 May 2026 14:30:23 +0100
Subject: [PATCH 14/26] SPV_EXT_split_barrier (#600)
* SPV_EXT_split_barrier
* Remove spurious capability
---
include/spirv/unified1/spirv.bf | 3 +++
include/spirv/unified1/spirv.core.grammar.json | 15 +++++++++------
include/spirv/unified1/spirv.cs | 3 +++
include/spirv/unified1/spirv.h | 13 ++++++++-----
include/spirv/unified1/spirv.hpp | 13 ++++++++-----
include/spirv/unified1/spirv.hpp11 | 13 ++++++++-----
include/spirv/unified1/spirv.json | 3 +++
include/spirv/unified1/spirv.lua | 3 +++
include/spirv/unified1/spirv.py | 3 +++
include/spirv/unified1/spv.d | 3 +++
10 files changed, 51 insertions(+), 21 deletions(-)
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 119ea89..0ecf295 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -1407,6 +1407,7 @@ namespace Spv
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
+ SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -2674,7 +2675,9 @@ namespace Spv
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 0f1b083..b2b665b 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -11253,27 +11253,29 @@
"version" : "None"
},
{
- "opname" : "OpControlBarrierArriveINTEL",
+ "opname" : "OpControlBarrierArriveEXT",
"class" : "Barrier",
+ "aliases" : [ "OpControlBarrierArriveINTEL" ],
"opcode" : 6142,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
- "capabilities" : [ "SplitBarrierINTEL" ],
+ "capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
- "opname" : "OpControlBarrierWaitINTEL",
+ "opname" : "OpControlBarrierWaitEXT",
"class" : "Barrier",
+ "aliases" : [ "OpControlBarrierWaitINTEL" ],
"opcode" : 6143,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
- "capabilities" : [ "SplitBarrierINTEL" ],
+ "capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
@@ -18591,9 +18593,10 @@
"version" : "None"
},
{
- "enumerant" : "SplitBarrierINTEL",
+ "enumerant" : "SplitBarrierEXT",
+ "aliases" : [ "SplitBarrierINTEL" ],
"value" : 6141,
- "extensions" : [ "SPV_INTEL_split_barrier" ],
+ "extensions" : [ "SPV_EXT_split_barrier", "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 7f66ede..06845bb 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -1406,6 +1406,7 @@ namespace Spv
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
+ SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -2673,7 +2674,9 @@ namespace Spv
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index 99b983c..964f5aa 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -1377,6 +1377,7 @@ typedef enum SpvCapability_ {
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilityBFloat16ConversionINTEL = 6115,
+ SpvCapabilitySplitBarrierEXT = 6141,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityArithmeticFenceEXT = 6144,
SpvCapabilityFPGAClusterAttributesV2ALTERA = 6150,
@@ -2608,7 +2609,9 @@ typedef enum SpvOp_ {
SpvOpCompositeConstructContinuedINTEL = 6096,
SpvOpConvertFToBF16INTEL = 6116,
SpvOpConvertBF16ToFINTEL = 6117,
+ SpvOpControlBarrierArriveEXT = 6142,
SpvOpControlBarrierArriveINTEL = 6142,
+ SpvOpControlBarrierWaitEXT = 6143,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpArithmeticFenceEXT = 6145,
SpvOpTaskSequenceCreateALTERA = 6163,
@@ -3497,8 +3500,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
- case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
- case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break;
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case SpvOpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break;
case SpvOpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break;
@@ -4515,7 +4518,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
- case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
+ case SpvCapabilitySplitBarrierEXT: return "SplitBarrierEXT";
case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case SpvCapabilityFPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA";
case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
@@ -5570,8 +5573,8 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL";
case SpvOpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL";
case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
- case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
- case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+ case SpvOpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT";
+ case SpvOpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT";
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case SpvOpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA";
case SpvOpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA";
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 966be25..655a79c 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -1373,6 +1373,7 @@ enum Capability {
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
CapabilityBFloat16ConversionINTEL = 6115,
+ CapabilitySplitBarrierEXT = 6141,
CapabilitySplitBarrierINTEL = 6141,
CapabilityArithmeticFenceEXT = 6144,
CapabilityFPGAClusterAttributesV2ALTERA = 6150,
@@ -2604,7 +2605,9 @@ enum Op {
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
@@ -3493,8 +3496,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
- case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
- case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break;
case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case OpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break;
case OpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break;
@@ -4511,7 +4514,7 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
- case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
+ case CapabilitySplitBarrierEXT: return "SplitBarrierEXT";
case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case CapabilityFPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA";
case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
@@ -5566,8 +5569,8 @@ inline const char* OpToString(Op value) {
case OpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL";
case OpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL";
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
- case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
- case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+ case OpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT";
+ case OpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT";
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case OpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA";
case OpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA";
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index bdc4ac0..270b33f 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -1373,6 +1373,7 @@ enum class Capability : unsigned {
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
+ SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -2604,7 +2605,9 @@ enum class Op : unsigned {
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
@@ -3493,8 +3496,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
- case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
- case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break;
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case Op::OpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break;
case Op::OpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break;
@@ -4511,7 +4514,7 @@ inline const char* CapabilityToString(Capability value) {
case Capability::AtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
case Capability::DebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case Capability::BFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
- case Capability::SplitBarrierINTEL: return "SplitBarrierINTEL";
+ case Capability::SplitBarrierEXT: return "SplitBarrierEXT";
case Capability::ArithmeticFenceEXT: return "ArithmeticFenceEXT";
case Capability::FPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA";
case Capability::FPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
@@ -5566,8 +5569,8 @@ inline const char* OpToString(Op value) {
case Op::OpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL";
case Op::OpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL";
case Op::OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
- case Op::OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
- case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
+ case Op::OpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT";
+ case Op::OpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT";
case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case Op::OpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA";
case Op::OpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA";
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index eb646f6..5a21f07 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -1339,6 +1339,7 @@
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
"BFloat16ConversionINTEL": 6115,
+ "SplitBarrierEXT": 6141,
"SplitBarrierINTEL": 6141,
"ArithmeticFenceEXT": 6144,
"FPGAClusterAttributesV2ALTERA": 6150,
@@ -2574,7 +2575,9 @@
"OpCompositeConstructContinuedINTEL": 6096,
"OpConvertFToBF16INTEL": 6116,
"OpConvertBF16ToFINTEL": 6117,
+ "OpControlBarrierArriveEXT": 6142,
"OpControlBarrierArriveINTEL": 6142,
+ "OpControlBarrierWaitEXT": 6143,
"OpControlBarrierWaitINTEL": 6143,
"OpArithmeticFenceEXT": 6145,
"OpTaskSequenceCreateALTERA": 6163,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index e425dd5..64b0a1f 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -1364,6 +1364,7 @@ spv = {
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
+ SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -2595,7 +2596,9 @@ spv = {
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index a35941b..5f3bae6 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -1335,6 +1335,7 @@ spv = {
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
'BFloat16ConversionINTEL' : 6115,
+ 'SplitBarrierEXT' : 6141,
'SplitBarrierINTEL' : 6141,
'ArithmeticFenceEXT' : 6144,
'FPGAClusterAttributesV2ALTERA' : 6150,
@@ -2538,7 +2539,9 @@ spv = {
'OpCompositeConstructContinuedINTEL' : 6096,
'OpConvertFToBF16INTEL' : 6116,
'OpConvertBF16ToFINTEL' : 6117,
+ 'OpControlBarrierArriveEXT' : 6142,
'OpControlBarrierArriveINTEL' : 6142,
+ 'OpControlBarrierWaitEXT' : 6143,
'OpControlBarrierWaitINTEL' : 6143,
'OpArithmeticFenceEXT' : 6145,
'OpTaskSequenceCreateALTERA' : 6163,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 8fa24b9..4e4e3dc 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -1409,6 +1409,7 @@ enum Capability : uint
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
+ SplitBarrierEXT = 6141,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
@@ -2676,7 +2677,9 @@ enum Op : uint
OpCompositeConstructContinuedINTEL = 6096,
OpConvertFToBF16INTEL = 6116,
OpConvertBF16ToFINTEL = 6117,
+ OpControlBarrierArriveEXT = 6142,
OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitEXT = 6143,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpTaskSequenceCreateALTERA = 6163,
--
2.54.0
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